(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method of fabricating a NAND flash memory device.
(2) Description of Prior Art
The objective of reducing device cell size to allow a greater number of smaller semiconductor chips to be obtained from a specific size starting substrate, has been positively influenced by the use of shallow trench isolation (STI), technology. The ability to form STI regions, comprised of insulator filled shallow trench shapes, allows the allotted space for the STI regions to be reduced when compared to LOCOS, (localized oxidation of silicon), counterparts, which consume more space and also produce undesirable xe2x80x9cbirds beakxe2x80x9d, or unwanted insulator extensions into subsequent active device regions. The smaller semiconductor chips, still comprised with device densities equal to, or greater than, counterpart, larger semiconductor chips, result in a decrease in the fabrication cost for a specific semiconductor chip as a result of obtaining a greater number of semiconductor chips from a specific size starting substrate. The smaller semiconductor chips, comprised with smaller features, also result in performances increases arising from reductions in performance degrading junction capacitance.
Flash memory devices have also been formed using STI regions, resulting in decreases in the cell size of these devices, allowing for integration of smaller, flash memory cells on a semiconductor substrate. However the coupling ratio of the flash memory device is reduced as the cell size becomes smaller. Higher coupling ratios allow more efficient read, write and erase cycles to achieved. The decrease in coupling ratio, when fabricating smaller cell size, flash memory devices, is attributed to less overlap between the control gate and the floating gate. This invention will describe a process for fabricating a flash memory cell, using STI regions, however compensating for the reduction in horizontal overlap between the control gate and the floating gate, by increasing the overlap between these structures vertically. Prior art, such as Ding et al, in U.S. Pat. No. 6,171,909, describe a process for increasing coupling ratio via use of vertical conductive spacers, formed on the sides of the floating gate structure. However that prior art does not describe key features used in this present invention, such as the simultaneous definition of the floating gate, and the conductive spacer features extending upwards from the edges of the underlying floating gate structure.
It is an object of this invention to fabricate high density, NAND flash memory devices having narrow pitch as a result of STI isolation.
It is another object of this invention to increase the coupling ratio of the NAND flash memory device via capacitance increases resulting from increased overlap between the control and floating gate structures.
It is still another object of this invention to simultaneously define a floating gate structure, and conductive vertical features protruding upward from the periphery of the floating gate structure, allowing increased overlap between an overlying control gate structure, and the floating gate structure comprised with the protruding vertical features, to be realized.
In accordance with the present invention a method of fabricating a flash memory device featuring the simultaneous definition of a floating gate structure, and conductive features protruding from upwards from the periphery of the floating gate structure, allowing increased overlap between a control gate, and the underlying floating gate structure to be realized, is described. After formation of STI regions, a tunnel insulator layer is grown on the region of a semiconductor substrate not occupied by the STI regions. A first conductive layer is deposited followed by definition of an insulator shape overlying the first conductive layer. A second conductive layer is deposited followed by an anisotropic dry etch procedure resulting in conductive spacers defined on the sides of the insulator shape, located overlying top portions of the underlying first conductive layer. The anisotropic dry etch procedure is continued to remove portions of the first conductive layer not covered by the insulator shape or by the conductive spacers, resulting in a floating gate structure featuring a base comprised from the first conductive layer and conductive spacers, formed from the second conductive layer, located on, and protruding upwards from, the floating gate base. Source/drain regions are next formed in regions of the semiconductor substrate not covered by the floating gate structure. After selective removal of the insulator shape a thin dielectric layer is formed on the floating gate structure. A third conductive layer is then deposited and defined to form a control gate structure on the underlying thin dielectric layer, resulting in a flash memory device featuring increased overlap between the control gate and floating gate structures as a result of the vertical protruding features of the floating gate structure.